Automatic test equipment (ATE), especially when used to test digital integrated circuits (ICs), increasingly face the challenge to test high-speed devices and to make sure that clean signals arrive at the device under test (DUT) and that signals provided by the DUT arrive undistorted at the location where the analysis circuits reside.
It should be noted that a DUT-Board (e.g. a circuit board providing for a connection between an ATE interface of an automatic test equipment and a device under test) is, in most cases, not designed, built or controlled by the ATE manufacturer. Thus, the characteristics of the DUT-Board are typically not known to the manufacturer of the ATE. However, the unknown characteristics or parameters of the DUT-Board can cause a severe impact on test accuracy and, finally, yield.
In the following, a typical digital ATE pin electronics will be described, making reference to FIG. 10.
In other words, FIG. 10 shows an extract from a schematic diagram of a typical digital ATE pin electronics. The pin electronics shown in FIG. 10 is designated in its entirety with 1000. Pin electronics 1000 comprises an output circuit 1010. The output circuit 1010 comprises a driver 1012. An output of the driver 1012 is coupled to a signal node 1020 via a resistor 1014. A signal present at the output of the driver 1012 is designated with SIG0, and a signal present at the signal node 1020 is designated with SIG. The pin electronics 1000 further comprises a comparator 1030, a first input of which is coupled to the signal node 1020. A second input of the comparator 1030 receives a threshold signal 1032, also designated as VTH. An output of the comparator 1030 is connected to a data input of a latch 1040. The latch 1040 receives a clock signal 1042, also designated as SCLK.
The signal node 1020 is coupled with a POGO pin 1050 via a transmission line or a cable 1060. The POGO pin is part of an ATE interface 1070. In a typical set-up, a DUT-Board is coupled with the POGO pin 1050 to provide an electrical connection between the ATE interface 1070 and a pin of a device under test (e.g. a package pin of an integrated circuit or a test pad of a printed circuit board). For this purpose, the DUT-Board typically comprises a transmission line (e.g. a strip line or a micro-strip line 1080). It should be noted here that it is assumed that the cable 1060 comprises a characteristic impedance ZT, and that the transmission line 1080 of the DUT-Board comprises a characteristic impedance ZD. Moreover, there is typically an impedance discontinuity at the ATE interface 1070. Apart from this, it should be noted that the cable 1060 and the transmission line 1080 typically comprise a frequency-dependent attenuation characteristic.
In the following, the operation of the pin electronics 1010 will be described, making reference to FIGS. 10 and 11.
FIG. 11 shows a graphical representation of signals present in the circuit 1000 of FIG. 10. The graphical representation of FIG. 11 is designated in its entirety with 1100. A first signal representation 1110 shows a temporal evolution of the signal SIG0 at the output of the driver 1020. A second signal representation 1120 describes a temporal evolution of a signal “POGO” at the ATE interface 1070. A third signal representation 1130 describes a temporal evolution of a signal SIG at the signal node 1020.
In the operation, the driver 1012 (D) produces a step signal SIG0, which is launched via a source impedance R (formed, for example, by the resistor 1014) into a transmission line, for example, the cable 1060. The cable 1060 ends at the ATE interface 1070, which is usually represented by POGO pins. From there (e.g. from the ATE interface), a DUT-Board connects the signal to the device under test 1074, e.g. via strip lines or micro-strip lines on a printed circuit board (DUT board).
The source impedance R is usually equal to the characteristic impedance ZT of the cable 1060. Advantageously, the impedance ZD of the DUT-Board traces 1080 is also the same (or at least similar).
Driver 1012 and series resistor 1014 are drawn as a symbol for any source. In other words, the source can be implemented as a current source with a parallel impedance.
At a point where the launch happens, the comparator 1030 is located. The comparator 1030 compares the present signal SIG with a static threshold VTH. A resulting digital signal, which is, for example, represented by a logic low when SIG<VTH and a logic high when SIG>VTH may further be digitally sampled with some sort of latch or flip-flop (S) and a tester clock.
Normal time-domain-reflection techniques have been applied using two different comparator threshold voltages to measure an unknown time-delay of the DUT-Board trace 1080 in order to deskew signals at and from the DUT. In this case, no device under test 1074 is inserted, so that the end of the DUT-Board trace 1080 is open.
FIG. 11 shows the signals, which are present when applying a conventional TDR concept. A step signal SIG0 is produced by the driver 1012 and is launched into the cable 1060 via the resister 1014. At the ATE interface 1070, a signal POGO can be observed. The signal SIG0 comprises an edge or step 1140. An edge or step 1142 of the signal POGO is a response to the edge or step 1140 caused by a wave traveling forward over the cable 1060. Due to a propagation delay on the cable 1060, the edge or step 1142 is delayed with respect to the edge or step 1140. A signal further travels along the transmission 1080. The open end (DUT) of the transmission line 1080 results in a reflection of the traveling wave. Consequently, the signal POGO exhibits a second edge or step 1144, which is caused by the reflection from the open end of the transmission line 1080.
The rise time of the edge 1144 is larger than the rise time of the edge 1142 due to a high frequency attenuation of the transmission line 1080.
The signal SIG at the signal node 1020 exhibits a first edge or step 1152 directly caused by the edge 1140 and a second edge or step 1154 caused by the reflection at the open end of the transmission 1080.
In other words, the first step 1152 of the signal SIG represents the driver's output and the second step 1154 of the signal SIG is the reflection from the open line 1080. The reflection step 1154 is slower (exhibits a longer rise time) than the first step 1152, because the reflection step 1154 has experienced an attenuation of traveling through the signal path (through the cable 1060 and the transmission line 1080) twice.
It should be noted here that the reflected waveform, namely the waveform of the second step 1154, is an exact representation of an attenuation of the signal path (consisting of the cable 1060 and the transmission line 1080). However, it is still a huge challenge to acquire an information about a time-domain-reflection response in an automated test equipment with reasonable effort.